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Forget the G5 - the talk is now all about IBM's Power 5, as Big Blue comes out to chat about the chip publicly for the first time, reports Computer Business. IBM will unwrap some of the features destined for its Power5 CPUs at the Hot Chips conference at Stanford University this week. IBM plans to have its Power5 chips ready for business in Q2 2004. Power5 features will include the addition of simultaneous multithreading (SMT). In the heat generation and power consumption department, IBM are looking to make its latest chip much cooler and more efficient than the Power4, the basis of Apple/IBM's PowerPC 970. Intel have developed similar implementations of SMT in the form of Hyperthreading for its Xeon processors, which are targeted at the server and workstation markets. However, IBM are planning more efficient means of implementing SMT in its Power5. Less sophisticated variants of SMT can also be found in earlier IBM 64-bit chips. Intel cites 30% performance improvements due to Hyperthreading technology. IBM may get closer to 35-40%, the article says. Another Power5 innovation is placing the main memory controller on the chip itself. IBM has said that its 'Squadron' servers which will quadruple the performance of its Power4-based servers, which were released in 2001. Big clock numbers aren't part of the equation: 1.5-2.0GHz for the Power5 and 2-3GHz for the Power5+. The Power5s will also support up to 64GB of main memory, versus 32GB for the Power4. All are destined for manufacture at IBM's brand new Fishkill fab. Analysis: If it weren't obvious already, stop counting clock cycles and start looking at processor bus and SMT. Even Intel, with its Centrino, has had to concede that, although in its marketing it's stressed the chip's 'low-power' use, rather than its relatively low clock speed.
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